Frontiers in Emerging Engineering & Technologies

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Frontiers in Emerging Engineering & Technologies

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Challenges in Verifying Test Pattern Generators for Modern Semiconductor Designs

Authors

  • Vikas Nagaraj MTS at Advanced Micro Device (AMD), San Jose, California, USA

Keywords:

ATPG (deterministic automatic test pattern generation), LBIST (LFSR stimulus / MISR response compaction), Test compression (decompressors, phase shifters, channel utilization), X-propagation control (X-masking / X-bounding for observability)

Abstract

The Modern SoEs are heterogeneous IP, tester I/O constraints, dynamically power-gated regions, and X-prone interfaces, and verification of SoESe Tunable TPG, therefore, is a multi-objective process of controllability, observability, aliasing, and power integrity. This work characterizes TPG verification as generating traces that provide a demonstration that patterns satisfy quantifiable targets below realistic clocks/resets/constraints/tester limits, and under five different kinds of TPGs: deterministic ATPG, LBIST (rereading/weighting), and compression-based TPGs. The approach integrates static DFT lint and formal BER properties, X-aware simulation and fault simulation, emulation, statistical confirmation (bootstrap confidence and MISR alias analysis), and power-aware vet and veto/scheduling. At three technology nodes, it has been observed that 96-channel otherwise-good distribution maintains ~99% stuck-at and ~94% transition coverage, reducing the pattern volume by ~38%; reseeded LBIST with 48-bit MISR may improve transition coverage and time; and selective bitwise X-masking may recover observability with minimal loss; and empirical results concerning alias behavior support theoretical alias behavior, and n=48 seems to be effective on complex designs. It documents Pareto improvements to coverage, safe toggle envelopes, and a silicon-correlation plan that aligns the coverage-driven modeling projections with ATE signatures. The result is a defensible sign-off contract-coverage with confidence intervals, alias-ppm targets mapped to MSR width, toggle/IR limits, constraint legality, equivalence proofs, ATE fit, and machine-readable manifest-making DFT verification defensible evidence.

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Published

2024-04-16

How to Cite

Vikas Nagaraj. (2024). Challenges in Verifying Test Pattern Generators for Modern Semiconductor Designs. Frontiers in Emerging Engineering & Technologies, 1(01), 49–73. Retrieved from https://irjernet.com/index.php/feet/article/view/176